Integrated circuit having an input voltage-clamping function and an input current-detecting function

ABSTRACT

An integrated circuit has an input voltage-clamping function and an input current-detecting function. A voltage-clamping circuit is provided for clamping a voltage at the input signal terminal, the voltage being clamped in response to an input current greater than a first predetermined value supplied to the input terminal. A current detecting circuit is also provided for detecting whether the input current supplied to the input terminal is greater than a second predetermined value, whereby the single input terminal for signals is used for both functions, i.e., the input voltage-clamping function and the input current-detecting function.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an integrated circuit. Moreparticularly, it relates to an integrated circuit having a limitednumber of I/0 terminals wherein two different functions are given to oneof the I/0 terminals by providing a simple circuit configuration. Thecircuit of the present invention is used, for example, as an input stageof an integrated logic circuit for driving a strobe light or anelectronic flash unit used with a camera.

2. Description of the Prior Art

In accordance with a recent increase in the degree of integration of anintegrated circuit, the number of I/0 terminals for an integratedcircuit chip has been increased. However, in order to mount the chip ona package, it is desired that the number of terminals be as few aspossible. Therefore, it is necessary, in an integrated circuit, that oneterminal have a plurality of functions. It is necessary especially in acircuit for connecting a camera to a strobe light unit mounted thereonbecause an increase of the number of terminals for connecting the camerato the strobe light unit is not preferable in view of the space.

SUMMARY OF THE INVENTION

It is, therefore, a primary object of the present invention to provideone terminal of an integrated circuit having a plurality of functions,by providing a simple circuit in the integrated circuit.

Another object of the present invention is to provide one terminal of anintegrated circuit having both the function of clamping the inputvoltage and the function of detecting the input current.

In order to achieve the above objects, there is provided an integratedcircuit having an input voltage-clamping function and an inputcurrent-detecting function, comprising: a signal input terminal forinput signals; an output terminal; a voltage-clamping circuit, connectedto the input terminal, for clamping a voltage at the input terminal, thevoltage being clamped while an input current supplied to the inputterminal is greater than a first predetermined value; acurrent-detecting circuit, connected to the voltage-clamping circuit,for detecting that the input current supplied to the input terminal isgreater than a second predetermined value and for providing a detectionsignal; and an output circuit, connected between the current-detectingcircuit and the output terminal, for providing an output signal at theoutput terminal in response to the detection signal.

BRIEF DESCRIPTION OF THE DRAWINGS

The above objects and advantages, as well as other features, of thepresent invention will be better understood from the followingdescription of the preferred embodiments with reference to theaccompanying drawings, wherein:

FIG. 1 is a circuit diagram illustrating of a camera system including aninput stage of an integrated circuit according to a first embodiment ofthe present invention;

FIG. 2A is a graph illustrating of the input current-input voltagecharacteristic of the circuit of FIG. 1;

FIG. 2B is a graph of the input current-output voltage characteristic ofthe circuit of FIG. 1;

FIG. 3 is a circuit diagram of a reference voltage source which mayalternatively be used in the circuit of FIG. 1, according to a secondembodiment of the present invention; and

FIGS. 4 and 5 are circuit diagrams illustrating of input stages ofintegrated circuits according to a third embodiment and a fourthembodiment of the present invention, respectively.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 is a camera system for explaining a first embodiment of thepresent invention. In FIG. 1, ST is an input stage of an integratedcircuit in a strobe light unit, namely an electronic flash unit; and CMis a camera including an automatic shutter-control circuit whichcontrols shutter speed in accordance with the brightness of an object tobe photographed. The input stage ST comprises a voltage-clamping circuit1 connected to an input terminal IN, a current-detecting circuit 2, andan output circuit 3. The voltage-clamping circuit 1 functions to clampthe input voltage to a predetermined voltage. It comprises a PNPtransistor Q₁, a first NPN transistor Q₃, a reference voltage sourceV_(R1), a second NPN transistor Q₄, and a diode Q₅. The PNP transistorQ₁ has a base connected to the input terminal IN, an emitter connectedto a negative terminal A of the reference voltage source V_(R1), and acollector connected to ground. The first NPN transistor Q₃ has a baseconnected to a positive terminal B of the reference voltage sourceV_(R1), a collector connected to a power supply line V_(CC), and anemitter. The second NPN transistor Q₄ has a base connected to theemitter of the first NPN transistor Q₃, a collector connected to theinput terminal IN, and an emitter connected to ground. The diode Q₅ hasan anode connected to the emitter of the first transistor Q₃ and acathode connected to ground.

The current-detecting circuit 2 functions to compare an emitter currentI₃ of the first NPN transistor Q₃ with a reference current I₀. Itcomprises a third NPN transistor Q₆ and a first current source CS₁ forsupplying the constant current I₀ and connected between the collector ofthe third NPN transistor Q₆ and the power supply line V_(CC). The baseof the third NPN transistor Q₆ is commonly connected to the emitter ofthe transistor Q₃, the base of the transistor Q₄, and the anode of thediode Q₅. The emitter of the transistor Q₆ is grounded.

The output circuit 3 comprises a fourth NPN transistor Q₇ having a baseconnected to the collector of the third NPN transistor Q₆, an emitterconnected to the ground, and a collector connected to an output terminalOUT. The collector of the transistor Q₇ is connected through a loadresistor R_(L) to the power supply line V_(CC).

The diode Q₅ is obtained, for example, by short circuiting a base and acollector of an NPN transistor, wherein the base is the anode and theemitter is the cathode.

The reference voltage source V_(R1) comprises a second current sourceCS₂ for supplying a constant current I₁, a second diode Q₂ connected inseries with the current source CS₂, and resistors R₁ and R₂ connected inseries. The anode of the diode Q₂ is connected through the currentsource CS₂ to the power supply line V_(CC). The cathode of the diode Q₂is connected to the negative terminal A. The resistor, comprising theresistors R₁ and R₂ connected in series, is connected in parallel withthe diode Q₂. The connecting point between the resistors R₁ and R₂ isconnected to the positive terminal B. The diode Q₂ is also realized byshort circuiting a base and a collector of an NPN transistor. Assumethat the forward voltage drop across the diode Q₂ is V_(D). Then thevoltage V_(R) between the terminals A and B is

    V.sub.R =V.sub.D R.sub.2 /(R.sub.1 +R.sub.2)

It should be noted that the voltage V_(R) is lower than the voltageV_(D).

The camera CM comprises an automatic shutter-control circuit 4, aswitching NPN transistor Q₈, a diode Q₉, and a current source CS₃ whichsupplies a constant current greater than the reference current I₀. Theswitching transistor Q₈ has a collector connected to ground of theautomatic shutter-control circuit 4, an emitter connected to ground, anda base connected through the current source CS₂ to the power supply lineV_(CC). The diode Q₉ has an anode connected to the base of the switchingtransistor Q₈ and a cathode connected to the ground. The base of thetransistor Q₈ is to be connected through a switch SW to the inputterminal IN of the input stage ST of the integrated circuit in thestrobe light unit.

The operation of the camera will now be described when the camera CM isdisconnected from the input stage ST of the integrated circuit in thestrobe light unit. In this state, the switch SW is open and the basevoltage of the switching transistor Q₈ is clamped by the diode Q₉ to thevoltage V_(D), provided that the forward voltage drop across the diodeQ₉ is also V_(D). Since the base-emitter voltage of the transistor Q₈ inits conductive state is substantially equal to V_(D), the switchingtransistor Q₈ is on. Therefore, the automatic shutter-control circuit 4is in operation so that the camera CM is in an automatic shutter mode.In this state, the input stage ST is not supplied with an input current.

On the other hand, in the operation of the input stage ST of FIG. 1 whenthe input stage ST is separated from the Camera CM, the function ofclamping the input voltage will first be described with reference toFIG. 2A. Assume that the voltage applied to the input terminal IN isV_(I), the voltage between the terminals A and B of the referencevoltage source V_(R1) is V_(R), the base-emitter voltages of thetransistors Q₁ and Q₃ are V_(BE)(Q1) and V_(BE)(Q3), respectively, andthe anode-cathode voltage of the diode Q₅ which is formed by atransistor is V_(BE)(Q5). When the input current I_(I) is graduallyincreased, the input voltage V_(I) is also increased, as shown in FIG.2A. When the input current I_(I) reaches a predetermined value I_(X),the transistors Q₁ and Q₃ and the diode Q₅ are completely turned on sothat the input voltage V_(I) is clamped to a value nearly equal to aconstant value V_(c). The constant value V_(c) is determined as follows.When the input current I_(I) is greater than the predetermined valueI_(X), the following expression is obtained with respect to the positiveterminal B connected to the base of the transistor Q₃ :

    V.sub.I +V.sub.BE(Q1) +V.sub.R =V.sub.BE(Q3) +V.sub.BE(Q5) (1)

The base-emitter voltage of each transistor is nearly the same and isnearly equal to 0.7 V at room temperature. Therefore, the followingexpression (2) can be obtained:

    V.sub.BE(Q1) =V.sub.BE(Q3)=V.sub.BE(Q5) =V.sub.D           (2)

Thus, from the above expressions (1) and (2), the input voltage V_(I)can be expressed as:

    V.sub.I =V.sub.D -V.sub.R                                  (3)

Since V_(D) and V_(R) are constant values, the input voltage V_(I) isclamped to a constant voltage V_(C) =V_(D) -V_(R) when the input currentI_(I) is greater than the predetermined value I_(X), as illustrated inFIG. 2A. In other words, the transistors Q₁, Q₃, and Q₄ constitute anegative feedback circuit. Therefore, when the input voltage V_(I) tendsto rise above the constant voltage V_(C), the collector current of thetransistor Q₄ also increases so that the rise of the input voltage V_(I)is suppressed. Also, when the input voltage V_(I) tends to fall belowthe constant voltage V_(C), the collector current of the transistor Q₄decreases so that the fall of the input voltage V_(I) is suppressed.

Now, the function of detecting the input current I_(I) will be describedwith reference to FIG. 2B. Since the base-emitter voltage of thetransistor Q₄ is nearly equal to the anode cathode voltage of the diodeQ₅, the emitter current of the transistor Q₄ is nearly equal to thecathode current of the diode Q₅. Since the base current of eachtransistor is negligible, the input current I_(I), i.e., the collectorcurrent of the transistor Q₄, is nearly equal to the emitter current ofthe transistor Q₄. Also, since the base currents of the transistors Q₄and Q₆ are negligible, the emitter current I₃ of the transistor Q₃ isnearly equal to the cathode current of the diode Q₅. Accordingly, theexpression I_(I) =I₃ is obtained. Similarly, since the base-emittervoltage of the transistor Q₆ is equal to the anode-cathode voltage ofthe diode Q₅, the emitter current of the transistor Q₆ is equal to thecathode current of the diode Q₅ as long as the input current I_(I) isless than the reference current I₀, as will be described later. Becausethe base currents of the transistors Q₄ and Q₆ are negligible, thecathode current of the diode Q₅ is always equal to its anode current,which is the emitter current I₃ of the transistor Q₃, and the emittercurrent of the transistor Q₆ is nearly equal to its collector currentI₆. Therefore, as long as the emitter current I₃ is less than thereference current I₀, the expression I₃ =I₆ can be obtained. As aresult, as long as the input current I_(I) is less than the referencecurrent I₀, the following equation is obtained:

    I.sub.I =I.sub.3 =I.sub.6                                  (4)

The base of the output transistor Q₇ receives a current I₀ -I₆ =I₀-I_(I) so that the transistor Q₇ is in the on state. Therefore, as shownin FIG. 2B, when the input current I_(I) is less than the referencecurrent I₀, the output voltage at the output terminal OUT is at a lowlevel. When the input current I_(I) is increased so that it is greaterthan the reference current I₀, the output transistor Q₇ cannot receive abase current and therefore assumes the off state. Therefore, the outputvoltage V₀ is at a high level equal to the power supply voltage V_(CC).Thus, the current-detecting circuit 2 detects whether or not the inputcurrent I_(I) exceeds the reference current I₀ to change the outputterminal OUT from a high level potential to a low level potential.

Now, the relation between the camera CM and the strobe light unit willbe described. When the strobe light unit is disconnected from thecamera, the transistor Q₈ in the camera CM is on so that the automaticshutter-control circuit 4 is in an active state. Since the input currentI_(I) is smaller than the reference current I₀, the potential at theoutput terminal OUT is caused to be at a low level. Based on the lowlevel potential at the output terminal OUT, the strobe light unitdetermines that the strobe light unit is disconnected from the camera.

When the strobe light unit is connected to the camera CM, a current I₂from the current source CS₃ in the camera CM is supplied, as the inputcurrent I_(I), to the input terminal IN so that the input voltage V_(I)is clamped to a value lower than the voltage V_(D) by thevoltage-clamping circuit 1. By this clamping, the transistor Q₈ in thecamera CM is turned off. Based on the transistor Q₈ being off, thecamera determines that the camera CM is connected to the strobe lightunit. The current-detecting circuit 2 detects that the input currentI_(I), which is equal to I₂, is greater than the reference current I₀ soas to cause the output terminal OUT to be a high potential level. Basedon the high potential level at the output terminal OUT, the strobe lightunit determines that the strobe light unit is connected to the cameraand that the current I₂ is supplied from the camera.

As an alternative to the reference voltage source V_(R1) in the circuitof FIG. 1, any reference voltage source may be possible as long as itprovides a reference voltage lower than the base-emitter voltage of atransistor. FIG. 3 is a circuit diagram of a second embodiment of theinvention and is an example of a reference voltage source. In FIG. 3,the reference voltage source V_(R2) comprises the constant currentsource CS₂, a resistor R, and an NPN transistor Q₂. The collector of thetransistor Q₂ is connected, through the resistor R and the currentsource CS₂ connected in series with each other, to the power supply lineV_(CC). The output of the current source CS₂ is connected to the base ofthe transistor Q₂. The emitter and the collector of the transistor Q₂are connected to the negative terminal A and to the positive terminal B,respectively. Assume that the base-emitter voltage of the transistor Q₂is V_(D). Since the base current is negligible, the reference voltagebetween the terminals A and B is V_(D) -RI₁. From the expression (3),the clamped input voltage V_(C) in this case is: ##EQU1##

FIG. 4 is a circuit diagram of a third embodiment of the presentinvention. For the purpose of simplicity, only an input stage of anintegrated circuit is shown. The difference between the input stage ofFIG. 1 and the input stage of FIG. 4 resides only in thecurrent-detecting circuit. The current-detecting circuit 2' in thecircuit of FIG. 4 comprises PNP transistors Q₁₀ and Q₁₁ and thereference current source CS₁ for supplying a constant current I₀. ThePNP transistor Q₁₀ has a base and a collector commonly connected to thecollector of the transistor Q₃ in the voltage clamping circuit and anemitter connected to the power supply line V_(CC). The PNP transistorQ₁₁ has a base connected to the base of the transistor Q₁₀, an emitterconnected to the power supply line V_(CC), and a collector connected tothe base of the output transistor Q₇. The reference current source CS₁is connected between the collector of the transistor Q₁₁ and ground.

The voltage-clamping circuit 1 and the output circuit 3 are the same asthose in the circuit of FIG. 1. In the voltage-clamping circuit 1 ofFIG. 4, the reference voltage source is denoted by V_(R). The referencevoltage source V_(R) may be V_(R1) in the circuit of FIG. 1, V_(R2) inthat of FIG. 3, or any other reference voltage source which provides areference voltage lower than V_(D).

Since the voltage-clamping circuit 1 of FIG. 4 is the same as that ofFIG. 1, the function of clamping the input voltage to a predeterminedlevel in the circuit of FIG. 4 is the same as that of FIG. 1.

The function of detecting the input current in the circuit of FIG. 4 isas follows. Similar to the circuit of FIG. 1, the expression I_(I) =I₃is obtained. Because the base potentials of the PNP transistors Q₁₀ andQ₁₁ are equal, I₃ =I₁₁ is obtained. Therefore, I_(I) =I₁₁ is obtained.When the input current I_(I), which is equal to the collector currentI₁₁ of the transistor Q₁₁, is greater than the reference current I₀, acurrent I₁₁ -I₀ is supplied to the base of the output transistor Q₇ sothat the transistor Q₇ is turned on to provide a low voltage at theoutput terminal OUT. When the input current I_(I) is less than thereference current I₀, the output transistor Q₇ is not supplied withcurrent at its base so that the transistor Q₇ is in the off state andprovides a high voltage at the output terminal OUT.

FIG. 5 is a circuit diagram of a fourth embodiment of the presentinvention. In FIG. 5, in place of the current-detecting circuit 2' andthe output circuit 3 of FIG. 4, a current-detecting and output circuit 5is employed. The current-detecting and output circuit 5 comprises thecurrent source CS₁ connected between the collector of the transistor Q₃and the power supply line V_(CC) and a PNP transistor Q₁₂ having a baseconnected to the collector of the transistor Q₃, an emitter connected tothe power supply line V_(CC), and a collector connected to the outputterminal OUT.

Because the base current of the transistor Q₃ is negligible, thecollector current of the transistor Q₃ is nearly equal to its emittercurrent I₃. When the current I₃, which is equal to the input currentI_(I), is less than the reference current I₀, the base current I₃ -I₀ isnegative so that the transistor Q₁₂ is in the off state and provides alow voltage at the output terminal OUT. When the input current I_(I) isgreater than I₀, the transistor Q₁₂ is in the on state and provides ahigh voltage at the output terminal OUT. Thus, the current-detecting andoutput circuit 5 of FIG. 5 detects whether or not the input currentI_(I) exceeds the reference current I₀ and, if so, changes the outputterminal OUT from a low level potential to a high level potential.

The present invention is not only adapted to a camera system but also tovarious other integrated circuit systems in which reduced I/0 terminalsare required.

From the foregoing description, it will be apparent that, according tothe present invention, by providing a relatively simple circuitconfiguration in an integrated circuit, a single terminal of theintegrated circuit can be made to have two functions, i.e., an inputvoltage-clamping function and an input current-detecting function. Thus,the present invention is very effective for integrated circuits.

We claim:
 1. An integrated circuit having an input voltage-clampingfunction and an input current-detecting function, comprising:a singleinput terminal for receiving an input signal having a voltage and aninput current; an output terminal; a voltage-clamping circuit,operatively connected to said single input terminal, for clamping thevoltage at said single input terminal while the input current suppliedto said single input terminal is greater than a first predeterminedvalue; a current-detecting circuit, operatively connected to saidvoltage-clamping circuit, for detecting whether the input currentsupplied to said input terminal is greater than a second predeterminedvalue and for generating a detection signal when the input current isgreater than the second predetermined value; and an output circuit,operatively connected between said current-detecting circuit and saidoutput terminal, for providing an output signal at said output terminalin response to said detection signal.
 2. An integrated circuit as setforth in claim 1, wherein said voltage-clamping circuit comprises:afirst PNP transistor having a base operatively connected to said inputterminal, having a collector operatively connected to ground and havingan emitter; a first NPN transistor having a base, having an emitter andhaving a collector operatively connected to said current detectingcircuit, a reference voltage source, having a positive terminaloperatively connected to said base of said first NPN transistor andhaving a negative terminal operatively connected to said emitter of saidfirst PNP transistor, for providing a reference voltage lower than thebase-emitter voltage of said first NPN transistor; a second NPNtransistor having a collector operatively connected to said single inputterminal, having a base operatively connected to said emitter of saidfirst NPN transistor and having an emitter operatively connected toground; and a first diode having an anode operatively connected to saidemitter of said first NPN transistor, having a cathode operativelyconnected to ground and having an anode-cathode voltage equal to thebase-emitter voltage of said first NPN transistor.
 3. An integratedcircuit as set forth in claim 2, wherein said reference voltage sourcehas a power supply line and comprises:a second diode having a cathodeoperatively connected to said emitter of said first PNP transistor andhaving an anode; a first current source operatively connected betweenthe power supply line and the anode of said second diode; and tworesistors, operatively connected in series and forming a connectingpoint therebetween, for forming a single resistor operatively connectedin parallel with said second diode, said positive terminal of saidreference voltage source being operatively connected to the connectingpoint between said two resistors.
 4. An integrated circuit as set forthin claim 2, operatively connectable to a power supply line, wherein saidreference voltage source comprises:a third NPN transistor having anemitter operatively connected to said negative terminal, having acollector operatively connected to said positive terminal and having abase; a resistor operatively connected between said collector and baseof said third NPN transistor; and a first current source operativelyconnected between the power supply line and said base of said third NPNtransistor.
 5. An integrated circuit as set forth in claim 3 or 4,wherein said current-detecting circuit comprises:a second currentsource, operatively connected to said output circuit, for supplying aconstant current having the second predetermined value; and comparingmeans, operatively connected to said second current source and saidfirst NPN transistor, for comparing the emitter current of said firstNPN transistor with the constant current.
 6. An integrated circuit asset forth in claim 5, wherein said comparing means comprises a fourthNPN transistor having a base operatively connected to said base of saidsecond NPN transistor and said emitter of said first NPN transistor,having an emitter operatively connected to ground and having a collectoroperatively connected to said second current source.
 7. An integratedcircuit as set forth in claim 5, wherein said comparing meanscomprises:a second PNP transistor having an emitter operativelyconnected to the power supply line and having a base and collectorcommonly connected to said collector of said first NPN transistor; and athird PNP transistor having an emitter operatively connected to thepower supply line, having a base operatively connected to said base ofsaid second PNP transistor, and having a collector operatively connectedto said second current source.
 8. An integrated circuit as set forth inclaim 6, wherein said output circuit comprises:a load resistoroperatively connected to said output terminal and the power supply line;and a fifth NPN transistor having a base operatively connected to saidcollector of said fourth NPN transistor, having a collector operativelyconnected to said load resistor and having an emitter operativelyconnected to ground.
 9. An integrated circuit as set forth in claim 7,wherein said output circuit comprises:a load resistor operativelyconnected to the power supply line and said output terminal; and a fifthNPN transistor having a base operatively connected to said collector ofsaid third PNP transistor, having a collector operatively connected tosaid load resistor and having an emitter operatively connected toground.
 10. An integrated circuit as set forth in claim 3 or 4, whereinsaid current-detecting circuit and said output circuit comprises:asecond current source, operatively connected to said collector of saidfirst NPN transistor and to the power supply line, for supplying aconstant current having the second predetermined value; and a fourth PNPtransistor having an emitter operatively connected to the power supplyline, having a base operatively connected to the collector of said firstNPN transistor and having a collector operatively connected to saidoutput terminal.
 11. An integrated circuit as set forth in claim 8,wherein said integrated circuit is included in a strobe light unit to beconnected to a camera.
 12. An integrated circuit as set forth in claim9, wherein said integrated circuit is included in a strobe light unit tobe connected to a camera.